ECE496B/596B, Digital System Design with VHDL

The course is designed to teach VHDL, with emphasis on simulation and the synthesizable subset of VHDL.

Cadence Leapfrog plays an important role in the instruction, as it is the "first-line of defense" for the students to evaluate their understanding of both the VHDL language and their particular coded design solutions through compilation and simulation.

Various components of the course are available for viewing and download:

Course Material is Original Unpublished Work. Used by Permission of David M. Clark, Instructor.

Selected Homework Problems

Problems involve simulation and/or synthesis. Other Homework problems were assigned that involved understanding of elements within VHDL but did not require extensive tool usage and as such have been omitted from this page. (They consisted of collections of problems from the textbook in use.)

Course Syllabus

Available in pdf or online

Course Description

Available in pdf or online

About the Instructor

David is a part-time Lecturer at the University of Arizona for ECE 496B/596B, Digital System Design with VHDL. He is otherwise employed by Raytheon Missile Systems Company (RMSC) in Tucson where he uses VHDL on a daily basis to accomplish ASIC and FPGA design tasks. He has been using VHDL for about 6 years, and he teaches VHDL to RMSC employees as demand warrants.

Last Updated 05-22-98 by David M. Clark